The present invention relates to a processor retention assembly. More specifically, the invention provides for retaining a dual processor assembly in a computer chassis.
The mounting of a dual processor assembly in a computer chassis presents challenges. As the processors become faster in their ability to process information, they can also tend to become larger and hotter. Therefore, due to the larger physical size of the processor itself and the heat sink associated with the processor, the mounting of the processor assembly within the computer chassis can present problems. The mounting assembly should be comprised of a rugged structure that is sturdy enough to be able to support the processors such that the processors are not adversely affected by the shock and vibration forces that may be applied to the mounting assembly. However, the mounting assembly should also provide for ease of installation and removal of the processor assembly from the mounting assembly. Additionally, the mounting assembly should be able to be secured to the computer chassis without requiring an extensive amount of connection hardware.
All of these potentially competing design factors can result in an inefficient solution for mounting a dual processor assembly within a computer chassis. Prior solutions suffer drawbacks in one or more of the design considerations of strength, ease of installation/removal, and quantity of connection hardware. Therefore, it would be desirable to provide for an improved apparatus and method for mounting a dual processor assembly within a computer chassis.
A processor retention assembly is provided. An embodiment of the processor retention assembly includes a first dual processor retention module and a second dual processor retention module. A connecting member is attached to the first dual processor retention module at a first end and is attached to the second dual processor retention module at a second end. In accordance with another embodiment of the present invention, covers are hingedly attached to each of the first and second dual processor retention modules.